Optical Phased Array Driver with 64 Independent Channels
MCAD0641 is an optical phased array driver. It generates up to 64-channels of programmable square wave signal to realize the beam steering, and each channel can be controlled independently and activated at the same time.
The output driver capability could be configured to obtain the best response time by providing up to 16 different selections.
A unique diagnose circuit is also embedded to check that the short-circuit conditions of the optical phased array, and then the user could disable the failed channel selectively.
The built-in over-drive function can fasten the response time of the optical phased array. The square wave generator can run up to 78.12kHz with 8 different setting.
The SPI interface provides the maximum applicable flexibility of MCAD0641, and the controlled phase data is transmitted through SPI communication.
| Parameter | MIN | MAX | UNIT |
| Supply voltage (VDD) | -0.3 | 6.0 | V |
| Supply voltage (HVDD) | -0.3 | 15.0 | V |
| Supply voltage (VDD_IO) | -0.3 | 6.0 | V |
| Decouple output voltage (VDD_1P8V) | -0.3 | 6.0 | V |
| Logic input voltage (CS, SCLK, DIN, RST) | -0.3 | 6.0 | V |
| Logic output voltage (SYNC, DOUT, DATA_RD) | -0.3 | 6.0 | V |
| Driver output voltage (OUT [0] ~ OUT [63]) | -0.3 | 15 | V |
| COM | -0.3 | 15 | V |
| REF | -0.3 | 15 | V |
| Junction temperature range, TJ | -40 | 150 | ̊C |
| Storage temperature | -65 | 150 | ̊C |
| VALUE | UNIT | ||
| ESD (Electrostatic discharge) |
Human-body model, per ANSI/ESDA/JEDEC JS-001m, all pins | +/-2000 | V |
| Charged-device model (CDM), per JEDEC specification JESD22-C101, all pins | +/-500 | V |
| Items | Parameters | MIN | NOM | MAX | UNIT |
| Supply voltage range | VDD | 4.5 | 5.5 | V | |
| HVDD | 5 | 10 | 12 | V | |
| VDD_IO | 1.6 | 5.5 | V | ||
| Operating free-air temperature, TA | -40 | 25 | 85 | °C |
VDD = VDD_IO = 3.3V, HVDD = 10V, TA = -40~85°C (unless otherwise noted)
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
| SUPPLY CURRENT | ||||||
| IVDD | VDD supply current | VVDD = 5V, fOSC = 40 MHz | 3 | 6 | mA | |
| IVDD_IO | VDD_IO supply current | VVDD_IO = 3.3V | 3 | 6 | mA | |
| IHVDD | HVDD supply current | VHVDD = 10V, Fsw = 40 kHz | 5 | 10 | mA | |
| SUPPLY VOLTAGE | ||||||
| VVDD | VDD supply voltage range | 4.5 | 5.5 | V | ||
| VVDD_IO | VDD_IO supply voltage range | 1.6 | 5.5 | V | ||
| VHVDD | HVDD supply voltage range | 4.5 | 10 | 14.5 | V | |
| DIGITAL INPUTS/OUTPUTS (DIN, DOUT, SCLK, CS, SYNC) | ||||||
| VOL | Low-level output voltage | IOH = 4mA, VVDD_IO = 3.3V |
GND + 0.25 | V | ||
| VOH | High-level output voltage | IOH = -4mA, VVDD_IO = 3.3V | VDD_IO – 0.6 | V | ||
| VIH | High-level input voltage | VVDD_IO = 3.3V | 2.1 | V | ||
| VIL | Low-level input voltage | VVDD_IO = 3.3V | 1.1 | V | ||
| IOH | 4 | mA | ||||
| IOL | -4 | mA | ||||
| SQUARE WAVE DRIVER (OUT [0] ~ OUT [63]) | ||||||
| IDOH_OUT | Output source current | Programmable in register DRV_OUT_SET [2:0] = 3b001 | 20 | mA | ||
| IDOL_OUT | Output sink current | Programmable in register DRV_OUT_SET [2:0] = 3b001 | 20 | mA | ||
| tjitter | Period jitter, determined by system clock | 40 | ns | |||
| COUT_Para | OUT parasitic capacitance when output config to be Hi-Z mode | 0.5 | pF | |||
| COM, REF DRIVER | ||||||
| IDOH_LYR | COM/REF driver source current | Programmable in register DRV_LYR_SET [2:0] = 3b001 | 20 | mA | ||
| IDOL_LYR | COM/REF driver sink current | Programmable in register DRV_LYR_SET [2:0] = 3b001 | 20 | mA | ||
| CLYR_Para | Parasitic capacitance when output config to be Hi-Z mode | 30 | pF | |||
| RESET THRESHOLD | ||||||
| VRST_HI | Reset input high threshold | 1.2 | V | |||
| VRST_LI | Reset input low threshold | 0.4 | V | |||
| SYSTEM PERFORMANCE | ||||||
| VHVDD_UVLO_F | HVDD falling to trigger HVDD undervoltage lockout | Register programmable to be disabled, with 3% accuracy | 4.2 | |||
| VHVDD_UVLO_R | HVDD rising to exist HVDD undervoltage lockout | Register programmable to be disabled, with 3% accuracy | 5 | V | ||
| VHVDD_OVLO_R | HVDD rising to trigger HVDD overvoltage lockout | Register programmable to be disabled, with 3% accuracy | 15.5 | V | ||
| VHVDD_OVLO_F | HVDD falling to exist HVDD overvoltage lockout | Register programmable to be disabled, with 3% accuracy | 15 | V | ||
| fCLK | Square wave driver clock frequency | Add external OSC as option | 38 | 40 | 42 | MHz |
| Vshort_th | Short detection threshold in self-test | 3.5 | V | |||
| tp | Driver propagation delay from SYNC active to 10% x HVDD, including 64 channels and COM | 1.25 | µs | |||
| tmismatch | Driver delay mismatch, including 64 channels and COM | 40 | ns | |||
| tsync | Minimum time of SYNC active | 0.5 | 1 | µs | ||
| tdata_ready | Data Ready pulse width | 4 | µs |
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
| SQUARE WAVE DRIVER (OUT [0] ~ OUT [63]) | ||||||
| tr | Driver rising time, 10% rises to 90% | Cload = 2.6nF, VHVDD = 5~12V | 1.25 | µs | ||
| tf | Driver falling time | Cload = 2.6nF, VHVDD = 5~12V | 1.25 | µs | ||
| SQUARE WAVE DRIVER (COM) | ||||||
| tr | Driver rising time | Cload = 10nF, VHVDD = 5~12V | 1.25 | µs | ||
| tf | Driver falling time | Cload = 10nF, VHVDD = 5~12V | 1.25 | µs | ||
| SPI INTERFACE | ||||||
| fSPI | SCLK frenquency | 40 | MHz | |||
| tCSSC | CS low to first SCLK, setup time | 10 | ns | |||
| tSPWH | SCLK pulse high level width | 11 | ns | |||
| tSPWL | SCLK pulse low level width | 11 | ns | |||
| tDIST | Setup time, DIN valid to SCLK falling edge | 5 | ns | |||
| tDIHD | Holdup time, valid DIN after SCLK falling edge | 5 | ns | |||
| tDOPD | SCLK rising edge to DOUT valid | 9 | ns | |||
| tCS | CS high pulse | 20 | ns | |||
| tCSDOD | CS low to DOUT driven | 10 | ns | |||
| tSCCS | Eighth SCLK falling edge to CS high | 10 | ns | |||
| tSDECODE | Command decode time | 4 | ns | |||
| tCSDOZ | CS high to DOUT Hi-Z | 20 | ns |
